Many electronic devices and systems include integrated circuits for the storage of data during the operation of the devices. For example, electronic devices such as computers, printing devices, scanning devices, personal digital assistants, calculators, computer work stations, audio and/or video devices, communications devices such as cellular telephones, and routers for packet switched networks may include memory in the form of integrated circuits for retaining data as part of their operation. Advantages of using integrated circuit memory compared to other forms of memory include space conservation and miniaturization, conserving limited battery resources, decreasing access time to data stored in the memory, and cutting the costs of assembling the electronic devices.
Dynamic Random Access Memory (“DRAM”) is an example of integrated circuit memory. DRAM typically comprises an array of semiconductor capacitor cells, each of which may hold an amount of electric charge that represents the logical value of a stored bit. The cells in the array are typically arranged in rows and columns. Each cell is situated at the intersection of a row and a column. Each cell in the DRAM array may be accessed by simultaneously addressing the intersecting row and column.
In operation, internal amplifiers in the DRAM sense the amounts of electric charges stored on the capacitors. Based on the sensed electric charges, the outputs of the sense amplifiers represent the logical values of the bits that are stored in the DRAM array. In this manner, the data stored in the array may be extracted from the DRAM integrated circuit for use by other integrated circuits in the electronic device. In addition, other internal circuitry on the DRAM refreshes the charge on those cells that the sense amplifiers have determined to already hold an electric charge. In this manner, the DRAM compensates for leakages of electric charge from the semiconductor capacitor cells, such as leakage into the substrate of the DRAM integrated circuit. Such reading, writing, and maintaining of charge on the cells are substantial internal operations of the DRAM.
The sense amplifiers connect to the cells through bitlines, which comprise the columns of the DRAM. Before reading from a cell, the DRAM removes residual charge on the bitline that addresses the cell. The residual charge is left over from a previous reading of another cell that shares the same bitline. The DRAM equalizes the bitline by pre-charging the bitline to a common potential before reading from the cell. When the DRAM addresses the cell, the charge stored in the cell raises or lowers the potential of the bitline from the common potential, signifying the logic value of the bit stored in the cell.
Bitlines, however, have internal resistance, internal parasitic capacitance, and parasitic capacitance with other bitlines. The resistances and capacitances comprise an RC circuit whose time constant increases the equalization time for pre-charging the bitlines. If too large, the time constant results in a slower read time for the DRAM integrated circuit that limits the use of the DRAM integrated circuit in modern high-speed electronic devices. As clock speeds for DRAM integrated circuits increase, the minimum time between commands lessens and the equalization times for bitlines should likewise decrease. Therefore, there is a need for decreasing the pre-charge time for the bitlines.